The present invention relates to a signal processing arrangement including at least one processing device with a series of interconnected processing cells which are each able to calculate a same function of three periodic variables m, n and p which are applied to first, second and third inputs of said cell which further has a first output connected lto the first input of a following cell considered in this direction from a first cell to a last cell and a second output on which appears the result of said calculation, said variable being the result of a previous calculation and corresponding variables applied to said cell and provided by said cells being successively time shifted with respect to one another.
Such a processing arrangement and more particularly a systolic processor is already known from the article "Let's Design Algorithms for VLSI Systems" by H.T. Kung, Caltech Conference on VLSI, January 1979, pp. 65 to 90 and more particularly pp. 74--78.